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PRELIMINARY
W215B
Notebook PC System Frequency Generator for K6 Processors
Features
* Generates system clocks for CPU, IOAPIC, SDRAM, PCI, USB plus 14.318 MHz (REF0:1) * MODE input pin selects optional power management input control pins (reconfigures pins 26 and 27) * Two fixed outputs separately selectable as 24-MHz or 48-MHz (default = 48-MHz) * VDDQ3 = 3.3V5%, V DDQ2 = 3.3V5% * Uses external 14.318-MHz crystal * Available in 48-pin TSSOP (6.1-mm) * 10 CPU output impedance Table 1. Pin Selectable Frequency 95/100_SEL 0 1 CPU, SDRAM Clocks (MHz) 95.0 100.0 PCI Clocks CPU/3 CPU/3
Block Diagram
VDDQ3 REF0 X1 X2 XTAL OSC PLL Ref Freq VDDQ2 IOAPIC VDDQ2 CPU0 CPU_2.5# CPU1 Stop Output Control CPU2 CPU3 VDDQ3 SDRAM0 SDRAM1 SDRAM2 95/100_SEL PLL 1 SDRAM3 SDRAM4 SDRAM5 SDRAM6/CPUSTOP# SDRAM7/PCISTOP# PCI_F Stop Output Control PCI0 PCI1 PCI2 PWR_DWN# Power Down Control PCI3 PCI4 PCI5 PLL2 48/24MHZ 48/24MHZ REF1
Pin Configuration
REF1 REF0 GND X1 X2 MODE VDDQ3 PCI_F PCI0 GND PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 GND 95/100_SEL Reserved Reserved VDDQ3 48/24MHZ 48/24MHZ GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ3 CPU_2.5# VDDQ2 IOAPIC PWR_DWN# GND CPU0 CPU1 VDDQ2 CPU2 CPU3 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6/CPU_STOP# SDRAM7/PCI_STOP# VDDQ3
W215B
MODE
I/O Control
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 December 27, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPU0:3 Pin No. 42, 41, 39, 38 9, 11, 12, 13, 14, 16 8 Pin Type O Pin Description
W215B
CPU Outputs 0 through 3: These four CPU outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Bus Outputs 0 through 5: These six PCI outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Free Running PCI Output: Unlike PCI0:5 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. SDRAM Clock Outputs 0 through 5: These six SDRAM clock outputs run synchronous to the CPU clock outputs. Output voltage swing is controlled by voltage applied to VDDQ3. SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has dual functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the CPU_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 6. Regarding use as a CPU_STOP# input: When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 are started beginning with a full clock cycle (2-3 CPU clock latency). Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage applied to VDDQ3. SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has dual functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the PCI_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 7. PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW after completing a full clock cycle. When brought HIGH, clock outputs PCI0:5 are started beginning with a full clock cycle. Clock latency provides one PCI_F rising edge of PCI clock following PCI_STOP# state change. Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage applied to VDDQ3. I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. 48-MHz / 24-MHz Output: Fixed clock outputs that default to 48 MHz following device power-up. Either or both can be changed to 24 MHz through use of the serial data interface (Byte 0, bits 2 and 3). Output voltage swing is controlled by voltage applied to VDDQ3 Fixed 14.318-MHz Outputs 0 through 1: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. REF0 is stronger than REF1 and should be used for driving ISA slots. Set to logic 1 for 3.3V CPU I/O. 95- or 100-MHz Input Selection: Selects power-up default CPU clock frequency as shown in Table 1 on page 1 (also determines SDRAM and PCI clock frequency selections). Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected.
PCI0:5
O
PCI_F
O
SDRAM0:5
36, 35, 33, 32, 30, 29 27
O
SDRAM6/ CPU_STOP#
I/O
SDRAM7/ PCI_STOP#
26
I/O
IOAPIC 48/24MHz
45 22, 23
O O
REF0:1
2, 1
O
CPU_2.5# 95/100_SEL
47 18
I I
X1
4
I
X2
5
I
2
PRELIMINARY
Pin Definitions
Pin Name PWR_DWN# Pin No. 44 Pin Type I Pin Description
W215B
Power-Down Control: When this input is LOW, device goes into a low-power standby condition. All outputs are actively held LOW while in power-down. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing a full clock cycle (2-4 CPU clock cycle latency). When brought HIGH, CPU, SDRAM, and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). Mode Control: This input selects the function of device pin 26 (SDRAM7/PCI_STOP#) and pin 27 (SDRAM6/CPU_STOP#). Refer to description for those pins. Power Connection: Power supply for PCI0:5, REF0:1, and 48-/24-MHz output buffers. Connected to 3.3V supply. Power Connection: Power supply for IOAPIC0, CPU0:3 output buffer. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane.
MODE VDDQ3 VDDQ2 GND
6 7, 15, 21, 25 28, 34, 48 46, 40 3, 10, 17, 24, 31, 37, 43 19, 20
I P P G
Reserved
I
Reserved Pins: Connect to Logic 1.
3
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter VDD, VIN TSTG TB TA ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection
W215B
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min.) Unit V C C C kV
DC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5% (3.135-3.465V), fXTL = 14.31818 MHz, VDDQ2 = 3.3V5% Parameter Description Test Condition Min. Supply Current IDDQ3 IDDQ2 Logic Inputs VIL VIH IIL IIH VOL VOH IOL Input Low Voltage Input High Voltage Input Low Current[2] Input High Current[2] Output Low Voltage Output High Voltage Output Low Current CPU0:3 SDRAM0:7 PCI_F, PCI0:5 IOAPIC REF0 REF1 48/24MHZ IOH Output High Current CPU0:3 SDRAM0:7 PCI_F, PCI0:5 IOAPIC REF0 REF1 48/24MHZ IOL = 2 mA IOH = -1 mA VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V 3.1 140 110 110 95 75 70 70 120 95 95 95 80 62 60 2.0 10 10 50 0.8 V V A A mV V mA mA mA mA mA mA mA mA mA mA mA mA mA mA Supply Current (3.3V) Supply Current (3.3V) CPU0:3 = 100 MHz Outputs Loaded[1] CPU0:3 = 100 MHz Outputs Loaded[1] 150 80 mA mA Typ. Max. Unit
Clock Outputs
Notes: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 2. W215B logic inputs have internal pull-up devices (not CMOS level).
4
PRELIMINARY
DC Electrical Characteristics (continued) TA = 0C to +70C, VDDQ3 = 3.3V5% (3.135-3.465V), fXTL = 14.31818 MHz, VDDQ2 = 3.3V5%
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[3] Load Capacitance, Imposed on External Crystal[4] X1 Input Capacitance[5] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 VDDQ3 = 3.3V 1.65 14 28 5 6 7 Description Test Condition Min. Typ.
W215B
Max.
Unit V pF pF pF pF nH
Pin Capacitance/Inductance
Notes: 3. X1 input threshold voltage (typical) is VDDQ3/2. 4. The W215B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
AC Electrical Characteristics (Lump Load Model)
TA = 0C to +70C, VDDQ3 = 3.3V5% (3.135-3.465V) fXTL = 14.31818 MHz, VDDQ2 = 3.3V5% AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.
Test Point
FTG
*20pF for CPU, REF1, IOAPIC, 24MHz & 48MHz *30pF for SDRAM & PCI
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 100 MHz Parameter tP f tH tL tR tF tD tJC tSK fST Period Frequency, Actual High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Description Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 10 1 1 45 50 Min. Typ. 10 100 5 5 4 4 55 500 250 3 Max. Unit ns MHz ns ns V/ns V/ns % ps ps ms
Zo
5
PRELIMINARY
SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF)
W215B
CPU = 100 MHz Parameter tP f tR tF tD tJC tSK tSK fST Period Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to SDRAM Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Description Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 16 100 1.5 3 1 1 45 50 Min. Typ. 10 100 4 4 55 500 Max. Unit ns MHz V/ns V/ns % ps ps ns ms
Zo
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF) CPU = 100 MHz Parameter tP f tH tL tR tF tD tJC tSK tO fST Description Period Frequency, Actual High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 1 Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V 12 12 1 1 45 50 4 4 55 500 250 4 3 Min. Typ. 30 33.3 Max. Unit ns MHz ns ns V/ns V/ns % ps ps ns ms
Zo
6
PRELIMINARY
I/O APIC Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 Test Condition/Comments Frequency generated by crystal oscillator 1 1 45 50 Min. Typ. 14.31818 4 4 55
W215B
Max.
Unit MHz V/ns V/ns % ms
1.5
Zo
REF0 Clock Output (Lump Capacitance Test Load = 45 pF) CPU = 100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 16 Test Condition/Comments Frequency generated by crystal oscillator 1 1 45 50 Min. Typ. 14.318 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
REF1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 Test Condition/Comments Frequency generated by crystal oscillator 0.5 0.5 45 Min. Typ. 14.318 2 2 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
7
PRELIMINARY
48-/24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 100 MHz Parameter m/n tR tF tD fST Description PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 50 Test Condition/Comments Min. Typ. 57/17
W215B
Max. 2 2 55 3
Unit V/ns V/ns % ms
Zo
AC Electrical Characteristics (Transmission Line Model)
TA = 0C to +70C, VDDQ3 = 3.3V5% (3.135-3.465V), fXTL = 14.31818 MHz, VDDQ2 = 3.35% AC clock parameters are tested and guaranteed over stated operating conditions using the stated transmission line load at the clock output.
22 Ohm 6 in ch e s 6 0 O h m tra ce
FTG
CPU Clock Outputs, CPU0:3 (Test Load: R = 33; C = 22 pF) CPU = 100 MHz Parameter tP f tH tL tR tF tD tJC tSK fST Period Frequency, Actual High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Description Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 10 1 1 45 50 Min. Typ. 10 100 5 5 4 4 55 250 250 3 Max. Unit ns MHz ns ns V/ns V/ns % ps ps ms
Zo
8
PRELIMINARY
SDRAM Clock Outputs, SDRAM0:7 (Test Load: R = 22; C = 22 pF)
W215B
CPU = 100 MHz Parameter tP f tR tF tD tJC tSK tSK fST Period Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to SDRAM Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Description Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 16 100 850 3 1 1 45 50 Min. Typ. 10 100 4 4 55 250 Max. Unit ns MHz V/ns V/ns % ps ps ps ms
Zo
PCI Clock Outputs, PCI0:5 (Test Load: R = 22; C = 22 pF) CPU = 100 MHz Parameter tP f tH tL tR tF tD tJC tSK tO fST Description Period Frequency, Actual High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 1 Test Condition/Comments Measured on rising edge at 1.5V Determined by PLL divider ratio Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V 12 12 1 1 45 50 4 4 55 250 250 4 3 Min. Typ. 30 33.3 Max. Unit ns MHz ns ns V/ns V/ns % ps ps ns ms
Zo
9
PRELIMINARY
I/O APIC Clock Output (Test Load: R = 33; C = 22 pF) CPU = 100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 Test Condition/Comments Frequency generated by crystal oscillator 1 1 45 50 Min. Typ. 14.31818 4 4 55
W215B
Max.
Unit MHz V/ns V/ns % ms
1.5
Zo
REF0 Clock Output (Test Load: R = 33; C = 22 pF) CPU = 100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 16 1 1 45 50 Min. Typ. 14.318 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
REF1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 Test Condition/Comments Frequency generated by crystal oscillator 0.5 0.5 45 Min. Typ. 14.318 2 2 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
10
PRELIMINARY
48-/24-MHz Clock Output (Test Load: R = 33; C = 22 pF) CPU = 100 MHz Parameter m/n tR tF tD fST Description PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 50 Test Condition/Comments Min. Typ. 57/17
W215B
Max. 2 2 55 3
Unit V/ns V/ns % ms
Zo
Ordering Information
Ordering Code W215B Document #: 38-00886 Package Name X Package Type 48-pin TSSOP (6.1 mm)
11
PRELIMINARY
Layout Example
+3.3V Supply FB
VDDQ3
W215B
+2.5V Supply FB
VDDQ2
10 F 0.005 F 10 F
C4
0.005 F
C3
C1 G G
C2
G
G
G
G
VDDQ3
5
C5 G
G C6
1G 2 3 4 5G 6 7V 8G 9 10 G 11 12 13 14 G 15 V 16 G 17 18 19 20 G 21 22 23 24 G
48 47 V 46 G 45 44 43 42 G 41 V 40 G 39 38 37 36 G 35 VDDQ3 V Core 34 G 33 32 G 31 30 G 29 V 28 G 27 26 V 25 G
G
G
C1
C2
G
G
FB = Dale ILB1206 - 300 (300 @ 100 MHz) C1 & C3 = 10-22 F C2 & C4 = 0.005 F C5 = 47 F C6 = 0.1 F
G = VIA to GND plane layer
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
12
W 215B
G
G
G
PRELIMINARY
Package Diagram
48-Pin Small Shrink Outline Package (TSSOP, 6.1 mm)
W215B
8
7
6
5
4
3
2
1
4 B 1.00 1.00 DIA. 0.00 DEEP 0.05
REV.
DESCRIPTION
DAT E
ORIGINATOR
00
C
1 2 3
INITIAL RELEASE PER DCN# D24479. INITIAL RELEASE PER DCN# D24860.
E
01
3
2
1
10/23 1996 03/18 1997
D.T.R. D.T.R.
E
H/2 E/2 1.00 E 8 H C L
0.20
H C
A-B A-B
D D
N N
D
0.20
D
e/2 X X X = A AND B X = A AND B
7
D
4
SEE DETAIL "A"
A
4
TOP VIEW
END VIEW
BOTTOM VIEW
EVEN LEAD SIDES TOPVIEW
ODD LEAD SIDES TOPVIEW
b SEE DETAIL 'B'
bbb
MC A2
A-B
D
9 C A C WITH PLATING 8 b b1
C
0.05
C
H
3 e A1 D 5 SEATING PLANE
aaa
C
c1
c
SIDE VIEW
BASE METAL
B
B
SECTION "C-C"
SCALE: 120/1
(SEE NO TE 10)
0.25
PARTING LINE H SEATING PLANE
A
(O )C
C
L6
C
DECIMAL XX XXX XXXX
MATERIAL
ANGULAR
PROJEC TION
Anam Industrial Co., LTD. Seoul, Korea Amk or Elec tronics Irving, TX TITLE
Amk or/Anam Pilipinas, INC. Manila, Philippines Amk or Elec tronics Chandler, AZ
EXCELLENCE IN SEMICONDUCTOR ASSEMBLY AND TEST
APPROVALS DRAWN
DATE
G. KAYLOR
CHECKED
02/28 1996 02/28 1996 10/23 1996 10/23 1996
SIZE DWG. NO.
PACKAGE OUTLINE, 6.10mm BODY, TSSOP, AAWW
REV.
A
DETAIL "B" DETAIL 'A'
(SCALE: 30/1) (SCALE: 30/1) DAMBAR PROTRUSION
FINISH ENG'R RELEASED
M. CARTER D. ROMAN DO NOT SCALE DRAWING T. LLORENTE
A1
SCALE
38119 8/1
2
SHEET
01 1 OF 2
1
8
7
6
5
4
3
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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